aspiring vlsi design engineer
Harivallabh
Ashok
Hands-on experience in RISC-V SoC integration and EDA automation, building toward RTL design and functional verification roles in semiconductor engineering.
Profile
Currently pursuing a B.Tech in Electronics and Communication Engineering at Amrita Vishwa Vidyapeetham, Bangalore, with a CGPA of 7.58. Recently completed a VLSI design internship at the RISE Lab, IIT Madras, working on RISC-V SoC peripheral integration and automation frameworks. Looking for an 8th-semester project or internship at a semiconductor company to grow further in RTL design, functional verification, and SoC development.
Experience
VLSI Design Intern
RISE Lab, IIT Madras
May 2026 — Jul 2026
- Developed and enhanced a Python- and YAML-based automation framework for SoC peripheral integration, eliminating manual backend configuration.
- Debugged and resolved peripheral and SoC integration issues, validated designs by generating FPGA bitstreams, and verified functionality on the Nexys Video FPGA board.
- Built and validated multiple reusable peripheral configurations for deployment, improving the scalability and reliability of the SoC peripheral integration framework.
Projects
Sep 2025 — Apr 2026
Low-Cost VLSI Sorting Architectures
- Designed folded and parallel sorter architectures for low cost and high throughput.
- Developed RTL and testbench code for functional verification.
- Implemented on FPGA hardware and integrated with sensors for seismic activity detection.
RTLFPGAVerification
Apr 2026
APB-Based SPI Interface Design & Verification
- Designed an APB-based SPI Master Interface in Verilog with baud rate generation, shift register, and slave select logic.
- Built a layered SystemVerilog testbench with generator, driver, monitor, scoreboard, and functional coverage.
- Debugged timing, clock synchronization, and serial data alignment via waveform analysis.
VerilogSystemVerilogAPB / SPI
Jan 2025 — Apr 2025
AI Image & Video Classification System
- Built a deep learning model distinguishing AI-generated from human-made images and videos at 90% accuracy.
- Designed and trained a CNN–Decision Tree model for classification.
- Deployed as a local server-based web app using Python (Flask) and JavaScript.
PythonFlaskDeep Learning
Skills
HDLs
1Verilog
2SystemVerilog
Tools
1Vivado
2Xilinx ISE
3LTspice
4Keil MicroVision 4
5Proteus
6Arduino
Languages
1Python
2Embedded C
3Java
Expertise
1VLSI
2Embedded Systems
3Deep Learning
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